A vertical transistor is a type of transistor that is adapted for use in high power applications. An exemplary vertical transistor device is a vertical power metal-oxide field effect transistor (MOSFET), wherein a source and gate contact are located on a first surface of the vertical MOSFET device that is separated from a drain contact by a drift layer formed on a substrate. Vertical MOSFETs are sometimes referred to as vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Due to their vertical structure, the voltage rating of a power MOSFET is a function of the doping concentration and thickness of the drift layer. Accordingly, high voltage power MOSFETs may be achieved with a relatively small footprint.
FIG. 1 shows an exemplary vertical power transistor 10. The power transistor 10 includes a substrate 12, a drift layer 14 formed over the substrate 12, one or more junction implants 16 in the surface of the drift layer 14 opposite the substrate 12, and a junction gate field effect transistor (JFET) region 18 between each one of the junction implants 16. Each one of the junction implants 16 is formed by an ion implantation process, and includes a deep well region 20, a base region 22, and a source region 24. Each deep well region 20 extends from a corner of the drift layer 14 opposite the substrate 12 downwards towards the substrate 12 and inwards towards the center of the drift layer 14. The deep well region 20 may be formed uniformly or include one or more protruding regions. Each base region 22 is formed vertically from the surface of the drift layer 14 opposite the substrate 12 down towards the substrate 12 along a portion of the inner edge of each one of the deep well regions 20. Each source region 24 is formed in a shallow portion on the surface of the drift layer 14 opposite the substrate 12, and extends laterally to overlap a portion of the deep well region 20 and the base region 22, without extending over either. The JFET region 18 defines a channel width 26 between each one of the junction implants 16.
A gate oxide layer 28 is positioned on the surface of the drift layer 14 opposite the substrate 12, and extends laterally between a portion of the surface of each source region 24, such that the gate oxide layer 28 partially overlaps and runs between the surface of each source region 24 in the junction implants 16. A gate contact 30 is positioned on top of the gate oxide layer 28. Two source contacts 32 are each positioned on the surface of the drift layer 14 opposite the substrate 12 such that each one of the source contacts 32 partially overlaps both the source region 24 and the deep well region 20 of one of the junction implants 16, respectively, and does not contact the gate oxide layer 28 or the gate contact 30. A drain contact 34 is located on the surface of the substrate 12 opposite the drift layer.
In operation, when a biasing voltage below the threshold voltage of the power transistor 10 is applied to the gate contact 30, a junction between each deep well region 20 and the drift layer 14 is reverse biased, thereby placing the power transistor 10 in an OFF state. In the OFF state of the power transistor 10, any voltage between the source contacts 32 and the drain contact 34 is supported by the drift layer 14. Due to the vertical structure of the power transistor 10, large voltages may be placed between the source contacts 32 and the drain contact 34 without damaging the device.
FIG. 2 shows operation of the power transistor 10 when the device is in an ON state. When a positive biasing voltage is applied to the gate contact 30 of the power transistor 10, an inversion channel layer 36 is formed at the surface of the drift layer 14 underneath the gate contact 30, thereby placing the power transistor 10 in an ON state. In the ON state of the power transistor 10, current (shown by the shaded region in FIG. 2) is allowed to flow from each one of the source contacts 32 through the inversion channel layer 36 and into the JFET region 18 of the drift layer 14. Once in the JFET region 18, current flows downward through the drift layer 14 towards the drain contact 34. An electric field presented by junctions formed between the deep well region 20, the base region 22, and the drift layer 14 constricts current flow in the JFET region 18 into a JFET channel 38. At a certain distance from the inversion channel layer 36 when the electric field presented by the junction implants 16 is diminished, the flow of current is disturbed laterally, or spread out in the drift layer 14, as shown in FIG. 2, before reaching the drain contact 34.
When switching between the OFF state and the ON state, the power transistor 10 may require a large input current at the gate contact 30, which generally cannot be provided by a standard control signal. Accordingly, gate buffer circuitry is coupled to the gate contact 30 of the power transistor 10 in order to deliver the necessary current to operate the device. The gate buffer circuitry is adapted to accept a low-current control signal and deliver a high-current output signal for driving the gate contact 30 of the power transistor 10.
FIG. 3 shows the power transistor 10 coupled to conventional gate buffer circuitry 40 for switching the power transistor 10 between an OFF state and an ON state. The conventional gate buffer circuitry 40 is constructed on a semiconductor die that is discrete and separate from the die on which the power transistor 10 is formed. The conventional gate buffer circuitry 40 includes a first PMOS transistor device 42 and a second NMOS transistor device 44 surrounded by a gate buffer substrate 46. The first PMOS transistor device 42 includes a body region 48 that surrounds a first implant well 50 and a second implant well 52, such that the first implant well 50 and the second implant well 52 are laterally separated within the body region. A gate oxide layer 54 is located on the surface of the body region 48, such that the gate oxide layer 54 partially overlaps and runs between the first implant well 50 and the second implant well 52. A gate contact 56 is located on top of the gate oxide layer 54. A source contact 58 is located on the surface of the second implant well 52, and a drain contact 60 is located on a surface of the second implant well 50, such that neither the source contact 58 nor the drain contact 60 contact the gate oxide layer 54 or the gate contact 56.
The second NMOS transistor 44 is also located in the gate buffer substrate 46, and includes a first implant well 62 and a second implant well 64. A gate oxide layer 66 is located on the surface of the gate buffer substrate 46, such that the gate oxide layer 66 partially overlaps and runs between the first implant well 62 and the second implant well 64. A gate contact 68 is located on top of the gate oxide layer 66. A source contact 70 is located on the surface of the first implant well 62, and a drain contact 72 is located on the surface of the second implant well 64, such that the source contact 70 and the drain contact 72 do not contact the gate oxide layer 66 or the gate contact 68.
The gate contact 56 of the first PMOS transistor device 42 is coupled to an input node 74. The source contact 58 of the first PMOS transistor device 42 is coupled to a supply voltage VDD. The drain contact 60 of the first PMOS transistor device 42 is coupled to an output node 76. The gate contact 68 of the second NMOS transistor device 44 is coupled to the input node 74. The source contact 70 of the second NMOS transistor device 44 is coupled to ground. The drain contact 72 of the second NMOS transistor device 44 is coupled to the output node 76. The gate contact 30 of the power transistor 10 is coupled to the output node 76 of the conventional gate buffer circuitry 40 via a wire bond 78 or a similar connection.
FIG. 4 shows a circuit diagram illustrating the equivalent circuit for the power transistor 10 and the conventional gate buffer circuitry 40 shown in FIG. 3. As described above, the first PMOS transistor device 42 includes a source contact 58 coupled to a supply voltage VDD, a drain contact 60 coupled to an output node 76, and a gate contact 56 coupled to an input node 74. The second NMOS transistor device 44 includes a drain contact 72 coupled to the output node 76, a source contact 70 coupled to ground, and a gate contact 68 coupled to the input node 74. The gate contact 30 of the power transistor 10 is coupled to the output node 76 of the conventional gate buffer circuitry 40. The drain contact 34 of the power transistor 10 may be used as a switching input, and the source contact 32 of the power transistor 10 may be used as a switching output.
In operation, when a control voltage VIN below the threshold voltage of the second NMOS transistor device 44 is applied to the input node 74 of the conventional gate buffer circuitry 40, the first PMOS transistor device 42 is placed in an ON state of operation, while the second NMOS transistor device 44 is placed in an OFF state of operation. Accordingly, the supply voltage VDD is delivered to the gate contact 30 of the power transistor 10, thereby placing the power transistor 10 in an ON state of operation. In the ON state of operation of the power transistor 10, a signal placed at the source contacts 32 of the power transistor 10 is delivered to the drain contact 34.
When a control voltage VIN higher than the supply voltage VDD less the threshold voltage of the first PMOS transistor device 42 is applied to the input node 74 of the conventional gate buffer circuitry 40, the first PMOS transistor device 42 is placed in an OFF state of operation, while the second NMOS transistor device 44 is placed in an ON state of operation. Accordingly, the gate contact 30 of the power transistor 10 is grounded, thereby placing the power transistor 10 in an OFF state of operation. In the OFF state of operation of the power transistor 10, a signal placed at the source contacts 32 of the power transistor 10 is not delivered to the drain contact 34.
Because the power transistor 10 is discrete and separate from the conventional gate buffer circuitry 40, the wire bond 78 used to couple the power transistor 10 to the conventional gate buffer circuitry 40 must be of significant length. Due to the length of the wire bond 78, parasitic inductance is introduced between the output node 76 of the conventional gate buffer circuitry 40 and the gate contact 30 of the power transistor 10. The parasitic inductance causes distortion in the output signal of the power transistor 10 and reduces the switching speed of the device.
Accordingly, there is a need for gate buffer circuitry that is capable of delivering the necessary current for operation of a power transistor device while reducing distortion in the output signal of the power transistor and reducing switching times.